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FX803 audio signalling processor xtal/clock clock generator tone 1 out tone 2 out (rx) audio in command data reply data serial clock switched sum out low pass filter sum in sum out cal/cues out summing amplifier audio switch ou t audio switch in tone 2 generator cues / dtmf 2 low pass filter digital noise filter 1 c-bus interface and control logic rx filter switch audio switch summing switch cal/cues switch xtal v dd v bias v ss logic input interrupt chip select signal input bias digital noise filter 2 programable notone timer tone 1 generator 5- / 2-tone dtmf 1 programable (tx period) timer quality meter gate time generator frequency counter v bias cues cal input amplifier fig.1 FX803 audio signalling processor both tone generators can be individually placed into a power economical powersave mode. a general purpose logic input, interfacing directly with the status register, is provided. this could be used as an auxiliary method of routeing digital information to the m controller via the c-bus. the output frequencies are produced from data loaded to the device, with a programmable, general purpose, on-chip timer available to indicate the tone transmit periods. a dual tone multi-frequency (dtmf) output is obtained by combining the 2 independent output frequencies in the integral summing amplifier. this summing amplifier output is also available for level adjustment. tones produced by the FX803 can also be used in the dbs 800 system as modulation calibration inputs and for cue audio indications for the operator. received tones are measured and their frequency indicated to the m controller in the form of a received data word. a poor-quality or incoherent tone will, after a programmed period, indicate n oton e . the FX803 is a low-power, 5-volt cmos integrated circuit and is available in 24-pin dil cerdip and 24-pin/lead plastic smd packages. fx80 3 audio signalling processor as part of the dbs 800 system, this audio signalling processor will provide an inband tone signalling facility for pmr radio systems. signalling systems supported include selcall (ccir, zvei i, ii and iii, eea), 2-tone selcall and dual tone multi-frequency (dtmf) encode. using a non-predictive tone decoder and versatile encoders gives the FX803 the capability to work in any standard or non-standard tone system. this is a full-duplex device consisting of: l two individual tone generators and a programmable (tx) period timer. l a tone decoder with programmable n otone timer. l an on-chip summing amplifier. for use with single tone or selective call systems. under the control of th e m controller, via c-bus, the FX803 will encode and transmit a single or pair of audio tones, in the frequency range 208hz to 3khz, simultaneously, and detect, decode and indicate the frequency of non-predicted input tones in the frequency range 313hz to 6khz. publication d/803/ 6 a pr il 1998
2 pin number function xtal: the output of the on-chip clock oscillator. external components are required at this input when a xtal input is used. see figure 2. xtal/clock: the input to the on-chip clock oscillator inverter. a xtal or externally derived clock (f xtal ) should be connected here. see figure 2. reply data: the c-bus serial data output to the m controller. the transmission of reply data bytes is synchronized to the serial clock under the control of the chip select input. this 3-state output is held at high-impedance when not sending data to the m controller. see timing diagrams. chip select (cs): the c-bus data loading control function. this input is provided by the m controller. data transfer sequences are initiated, completed or aborted by the cs signal. see timing diagram. command data: the c-bus serial data input from the m controller. data is loaded to this device in 8-bit bytes, msb (b7) first, and lsb (b0) last, synchronized to the serial clock. see timing diagrams. logic input: this real-time input is available as a general purpose logic input port which can be read from the status register. see table 3. interrupt request (irq): the output of this pin indicates an interrupt condition to the m controller, by going to a logic 0. this is a wire-or able output, allowing the connection of up to 8 peripherals to 1 interrupt port on the m controller. this pin has a low-impedance pulldown to logic 0 when active and a high-impedance when inactive. the system irq line requires one pullup resistor to v dd . the conditions that cause interrupts are indicated in the status register and are shown below: g/purpose timer period expired n otone timer period expired rx tone measurement complete these interrupts are inactive during relevant powersave conditions and can be disabled by bits 5 and 6 in the control register. no internal connection, connect to v ss . no internal connection, connect to v ss . audio switch in: the input to the stand-alone, on-chip audio switch. this switching function (control register bit 7) may be used to break the system transmitter modulation path when it is required to provide a cue (beep) from tone generator 2 to the loudspeaker via the fx806 plmr audio processor. audio switch out: the output of the stand-alone, on-chip audio switch. v ss : negative supply (signal ground). j/lg/ls 1 2 3 4 5 6 7 8 9 10 11 12 dw 1 2 3 5 6 7 8 4 9 10 11 12
3 pin number function j/lg/ls 13 14 15 16 17 18 19 20 21 22 23 24 (rx) audio in: the received audio tone signalling input to the input amplifier. this input requires to be a.c. coupled and connected, using external components, to the signal input bias pin. see figure 2. signal input bias: external components are required between this input and the (rx) audio in pin see figure 2. v bias : the internal circuitry bias line, held at v dd /2 this pin must be decoupled to v ss by capacitor c 2 see figure 2. tone 1 out: tone 1 generator (2-/5- tone selcall or dtmf 1) output. external gain and coupling components will be required at this output when operating in a complete dbs 800 audio installation. the frequency of this output is determined by writing to tx tone generator 1 register (table 4). see figure 2. tone 2 out: tone 2 generator (2-/5- tone selcall, cues or dtmf 2) output. external gain and coupling components will be required at this output when operating in a complete dbs 800 audio installation. the frequency of this output is determined by writing to tx tone generator 2 register (table 5). see figure 2. cal/cues out: an auxiliary, selectable tone frequency output, providing a square wave calibration signal from tone 2 generator or a sine wave cues (beep) signal from the summing amplifier. the output mode (cal or cues) is selected by bit 14 in the tx tone generator 2 register (table 5). in a dbs 800 audio installation, this output should be connected to the calibration input of the fx806 plmr audio processor. when tone generator 2 is set to v bias (n otone ), the cal output is pulled to v bias and during a powersave of tone generator 2 it is held at v ss . sum in: the input to the on-chip summing amplifier. this amplifier is available for combining tone 1 and tone 2 outputs (dtmf). gain and coupling components should be used at this input to provide the required system gains. see figures 2 and 3. sum out: the output of the on-chip summing amplifier. combined tones (1 and 2) are available at this output. see figures 2 and 3. switched sum out: the combined tone output available for transmitter modulation. the switch allows control of the FX803 final output to the fx806. control of this switch is by bit 4 of the control register. see figures 2 and 3. no internal connection, connect to v ss . serial clock: the c-bus serial clock input. this clock, produced by the m controller, is used for transfer timing of commands and data to and from the audio signalling processor. see timing diagrams. v dd : positive supply rail. a single +5-volt power supply is required. levels and voltages within the audio signalling processor are dependent upon this supply. note: (i) further information on external components and dbs 800 system integration of this microcircuit are contained in the system support document. c-bus is cmls proprietary standard for the transmission of commands and data between a m controller and dbs 800 microcircuits. it may be used with any m controller, and can, if desired, take advantage of the hardware serial i/o functions embodied into many types of m controller. the c-bus data rate is determined solely by the m controller. dw 13 14 15 16 17 18 19 20 21 22 23 24
4 external components component value r 1 = 1.0m w r 2 2.0m w *r 3 100k w *r 4 82.0k w *r 5 122k w *r 6 100k w *r 7 100k w r 8 22.0k w notes 1. xtal/clock circuitry components shown inset are recommended in accordance with cml application note d/xt/1 april 1986. the dbs 800 system support document contains additional notes on the use of xtal/ clock frequencies (f xtal ). 2. it is recommended that, to improve screening and reduce noise levels around the FX803, pins 8, 9 and 22 are connected to v ss . 3. resistors marked with an asterisk (*) are system components, calculated to operate in a system with other dbs 800 microcircuits. figure 3 shows in detail, these components used in the system signal paths. r 3 , r 4 , r 5 , c 5 C tone mixing components to provide a 3db tone-differential (twist) when used in a dtmf configuration. single tone output levels are set independently or by the fx806 modulator drivers. r 7 C modulation level and matching for inputs to the fx806. fig.2 recommended external components + C sum out bias switched sum out cal cues cal/cues out tone 2 out tone 1 out sum in audio switch out audio switch in summing amplifier from fx806 main process out to fx806 sum in to fx806 calibration in dbs 800 transmit audio bus 17 16 19 20 21 18 11 10 fx80 3 part of fig.3 output signal switching v bias xtal/clock v dd v dd see inset below v ss audio switch in reply data serial clock 2 1 xtal/clock v ss inset FX803j r 1 x 1 command data audio switch out xtal signal bias (rx) audio in tone 1 out tone 2 out cal/cues out sum in sum out switched sum out v ss c 6 c 5 r 3 r 4 r 5 r 2 c 1 c 2 xtal c 3 c 4 r 7 * * * * * tone level and gain components 13 14 15 16 17 18 19 20 21 22 23 2 4 1 2 3 4 5 6 7 8 9 10 11 12 FX803j r 6 cs logic input v ss irq r 8 c 1 = 0.1 m f c 2 1.0 m f c 3 33.0pf c 4 33.0pf c 5 22.0pf c 6 1.0 m f x 1 f xtal 4.00mhz tolerance: r = 10% c = 20%
5 controlling protocol control of the FX803 audio signalling processor's operation is by communication between the m controller and the FX803 internal registers on the c-bus, using address/commands (a/cs) and appended instructions or data (see figure 7). the use and content of these instructions is detailed in the following paragraphs and tables. address/commands the first byte of a loaded data sequence is always recognized by the c-bus as an address/command (a/c) byte. instruction and data transactions to and from this device consist of an address/command byte followed by either: (i) further instructions or data or, (ii) a status or data reply. instructions and data are loaded and transferred, via c-bus, in accordance with the timing information given in figures 7 and 8. table 1 shows the list of a/c bytes relevant to the FX803. a complete list of dbs 800 c-bus address allocations is published in the system support document. (rx) high band frequency (hz) (tx) tone generators 1 and 2 (rx) extended band (rx) high band 0 1000 2000 3000 4000 5000 6000 208hz to 3000hz 1250hz to 6000hz 625hz to 3000hz 313hz to 1500hz (rx) mid band 0 1000 2000 3000 4000 5000 6000 frequency (hz) FX803 internal registers FX803 internal registers are detailed below: control register (30 h ) C write only, control and configuration of the FX803. status register (31 h ) C read only, reporting of device functions. rx tone frequency register (32 h ) C read only, indicates frequency of the last received input. rx n otone timer register (33 h ) C write only, setting of the rx n otone period. tx tone generator 1 register (34 h ) C write only, setting the required output frequency from tx tone generator 1. tx tone generator 2 register (35 h ) C write only, setting required output frequency from tx tone generator 2. general purpose timer register (36 h ) C write only, setting of a general purpose, sequential time period. command address/command (a/c) byte + data assignment hex. binary byte/s msb lsb general reset 01 0 0 0 00001 write to control register 30 0 0 1 10000 + 1 byte instruction to control register read status register 31 0 0 1 10001 + 1 byte reply from status register read rx tone frequency 32 0 0 1 10010 + 2 byte reply from rx tone register write to n otone timer 33 0 0 1 10011 + 1 byte instruction to n otone register write to tx tone gen. 1 34 0 0 1 10100 + 2 byte instruction to tx tone gen. 1 write to tx tone gen. 2 35 0 0 1 10101 + 2 byte instruction to tx tone gen. 2 write to g/purpose timer 36 0 0 1 10110 + 1 byte instruction to g/purpose timer table 1 c-bus address/commands fig.4 FX803 frequencies
6 status bits received first set to 0 set to 0 set to 0 set to 0 logic input status 1 0 g/purpose timer period expired (irq generated if enabled) (table 2) n otone timer period expired (irq generated if enabled) (table 2) rx tone measurement complete (interrupt generated) reading msb bit 7 0 6 0 5 0 4 0 3 1 0 2 1 1 1 0 1 read status register C a/c 31 h , followed by 1 byte of reply data. controlling protocol ...... table 3 status register interrupt requests (irq) interrupts on this device are available to draw the attention of the m controller to a change in the condition of the bit in the status register. however bits are set in the status register irrespective of the setting of interrupt enable bits (table 2) and these changes may be recognized by polling the register. general purpose timer period set to a logic 1 when the timer period has expired. cleared to a logic 0, i by a read of the status register or, ii new g/purpose timer information or, iii general reset command n otone timer period set to a logic 1 when the timer period has expired. cleared to a logic 0, i by a read of the status register or, ii new n otone timer information or, iii general reset command rx tone measurement set to a logic 1 when the rx tone measurement is complete. cleared to a logic 0, i by a read of the status register or, ii general reset command control bits transmitted first audio switch enable disable g/purpose timer interrupt enable disable decoder interrupts enable disable summing switch enable disable band selection high band mid band extended band do not use this setting set to 0 set to 0 setting msb bit 7 1 0 6 1 0 5 1 0 4 1 0 32 00 01 10 11 1 0 0 0 table 2 control register audio switch see the signal switching diagram (figure 3) and dbs 800 document for application examples. general purpose timer should be set up before interrupts are enabled, as a general reset command will set the timer period to 00 h C 0ms (permanent interrupt). interrupt enable instructions status bits 0, 1 and 2 are produced regardless of the state of these settings. band selection bits 2 and 3 set the required frequency range (see figure 4, FX803 frequencies). summing switch to break the FX803 drive to the fx806 plmr audio processor (see figure 3, signal switching). interrupt designation decoder interrupts: no tone timer and rx tone measurement. transmitter interrupt: g/purpose timer interrupt. write to control register C a/c 30 h , followed by 1 byte of command data.
7 controlling protocol ...... tx tone generator registers 1 and 2 each tx tone generator is controlled individually by writing a two-byte command to the relevant tx tone generator register. the format of this command word, which is different for each tone generator, is shown below with the calculations required for tone frequency (f tone ) generation described in the following text. write to tx tone generator 1 register C a/c 34 h followed by 2 bytes of command data. tx tone frequencies with reference to tables 4 and 5 (above), whilst input data words a or b can be programmed for frequencies outside the stated limits of 208hz and 3000hz, any output frequencies obtained may not be within specified parameters (see specification page). calculations as can be seen from tables 4 and 5 (above), a binary number (a or b C bits 0 to 12) is loaded to the respective tx tone generator. the formulas shown below are used to calculate the required output frequency. required tx tone output frequency = f tone 1 or 2 x tal /clock frequency = f xtal input data word (bits 0 to 12) = a or b formula f tone (h z ) =f xtal (h z ) or input a (or b) =f xtal (h z ) 4 x a (or b) 4 x f tone (h z ) msb bit numbers lsb (loaded first) (loaded last) 1514 13 1211109876543210 0 0 v bias / these 13 bits (0 to 12) are used to produce a binary number, designated a . enable a is used in the formulas below to set the tx tone 1 frequency (f tone 1). msb bit numbers lsb (loaded first) (loaded last) 1514 13 1211109876543210 0 cal/ v bias / these 13 bits (0 to 12) are used to produce a binary number, designated b . cues enable b is used in the formulas below to set the tx tone 2 frequency (f tone 2). write to tx tone generator 2 register C a/c 35 h followed by 2 bytes of command data. table 5 setting tx tone generator 2 table 4 setting tx tone generator 1 notes (1) programming tone generator 2 to v bias (n otone ) (bit 13) will place the cal/cues output at v bias via a 40k w internal resistor. (2) programming tone generator 2 to powersave will place the cal/cues output at v ss . (3) if both tone generators (1 and 2) are powersaved, the summing amplifier is also powersaved. the binary number produced by bits 0 to 12 ( msb ) is designated "a." if a = all logic 0 then tx tone generator 1 is powersaved. bit 13 at logic 1 = tone 1 output at v bias (n otone ). 0 = tone 1 output enabled. bits 14 and 15 ( msb ) must be logic 0. bit 13 at logic 1 = tone 1 output at v bias (n otone ). 0 = tone 1 output enabled. bit 14 at logic 1 = squarewave cal output. 0 = sinewave cues output. bit 15 ( msb ) must be a logic 0. the binary number produced by bits 0 to 12 ( msb ) is designated "b." if b = all logic 0 then tx tone generator 2 is powersaved.
8 controlling protocol ...... read rx tone frequency register C a/c 32 h , followed by 2 bytes of reply data. measurement of rx signal frequency (s input ) the measurement details given on pages 10 and 11 are for a xtal/clock frequency (f xtal ) of 4.032mhz, a scaling formula for other values of f xtal is given at the bottom of this page. the input audio signal (s input ) is filtered and measured in the frequency counter over a specified measurement period (9.125 ms or 18.250 ms). the measuring function counts the number of complete input cycles occurring within the measurement period and then the number of measuring-clock cycles necessary to make up the period. when the count period of a successful decode is complete, the rx tone measurement bit in the status register, and the interrupt bit (if enabled) are set. the rx tone frequency register will now indicate the signal frequency (s input ) in the form of 2 bytes (1 and 0) as illustrated in figure 6 below. measurement period r complete input cycle complete input cycle complete input cycle complete input cycle complete input cycle filtered audio input signal measuring clock cycles n input s 2 x the remainder (r) C byte 0 a binary number representing the remainder part, r, of 2 x input signal frequency (s input) . r = number of specified measuring-clock cycles required to complete the specified measurement period (see n). the clock-cycle frequencies are: high band decode = 56.00 khz = f mid band decode = 28.00 khz = f extended band decode = 56.00 khz = f fig.5 measurement of a mid or high band rx frequency the integer (n) C byte 1 a binary number representing twice the number of complete input audio cycle periods counted during the specified measurement period, which is: high band decode = 9.125 ms = t mid band decode = 18.250 ms = t extended band decode = 9.125 ms = t see the bottom of this page for t and f scaling factors 15 14 13 12 11 10 9 8 byte 0 (reply data ) (lsb) C transmitted las t integer (n) byte 1 0 0 remainder (r) (reply data) (msb) C transmitted first 0 0 76 54 321 0 fig.6 format of the rx tone frequency register f xtal scaling factors the calculations above are for an f xtal of 4.032mhz. the following formulas enable the calculation of these values using any xtal value. note: f xtal values are stated in mhz. t scaled = t x 4.032 f xtal f scaled = f x f xtal 4.032
9 controlling protocol ...... frequency measurement formul? to assist in the production of look-up tables and limit-values in the m controller and provide guidance upon the determination of n and r from a measured frequency, the following formul? show the derivation of the rx frequency, s input , from the measured data bytes (n and r), figure 6. n m and r m C mid band the measurement period = 18.250ms clock frequency = 28.000khz the measured frequency = 2 x s input c/s in the measurement period there are: 2 x s input x 18.250 x 10 -3 cycles nm is the lower integer value of this decimal number: nm = int (18.250 x 10 -3 x 2 x s input ) [6] rm is rounded to the nearest integer of this decimal number: rm = (18.250 x 10 -3 C nm ) x 28000 [7] 2 x s input s input C high band in the measurement period of 9.125ms, there are nh cycles at 2s input and rh clock cycles at 56.000khz. so nh + rh = 9.125ms 2 x s input 56000 from which s input = 28000 x nh hz [1] (511 C rh) n h and r h C high band the measurement period = 9.125ms clock frequency = 56.000khz the measured frequency = 2 x s input c/s in the measurement period there are: 2 x s input x 9.125 x 10 -3 cycles nh is the lower integer value of this decimal number: nh = int (9.125 x 10 -3 x 2 x s input ) [4] rh is rounded to the nearest integer of this decimal number: rh = (9.125 x 10 -3 C nh ) x 56000 [5] 2 x s input high band measurement s input C mid band in the measurement period of 18.250ms, there are nm cycles at 2s input and rm clock cycles at 28.000khz. so nm + rm = 18.250ms 2 x s input 28000 from which s input = 14000 x nm hz [2] (511 C rm) mid band measurements n e and r e C extended band the measurement period = 9.125ms clock frequency = 56.000khz the measured frequency = s input c/s in the measurement period there are: s input x 9.125 x 10 -3 cycles ne is the lower integer value of this decimal number: ne = int (9.125 x 10 -3 x s input ) [8] re is rounded to the nearest integer of this decimal number: re = (9.125 x 10 -3 C ne ) x 56000 [9] s input s input C extended band in the measurement period of 9.125ms, there are ne cycles at s input and re clock cycles at 56.000khz. so ne + re = 9.125ms s input 56000 from which s input = 56000 x ne hz [3] (511 C re) extended band measurements
10 controlling protocol ...... write to the rx n otone timer register C a/c 33 h followed by 1 byte of command data. setting msb 76 5 4 00 0 0 321 0 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 function/period transmitted bit 7 first these 4 bits must be 0 high/extended mid band band period (ms) 00 " 20 1% 40 1% 40 " 80 " 60 " 120 " 80 " 160 " 100 " 200 " 120 " 240 " 140 " 280 " 160 " 320 " 180 " 360 " 200 " 400 " 220 " 440 " 240 " 480 " 260 " 520 " 280 " 560 " 300 " 600 " operation of the rx n otone timer an rx n otone period is that period when no signal or a consistently bad-quality signal is received. the rx n otone timer can be employed to indicate to the m controller that a n otone situation has existed for a predetermined period. this timer register can be written-to and set in any mode of the FX803. the n otone timer period is primed by writing to the n otone timer register (33 h ) using the settings given in table 6. priming sets the timing period; this period can only start directly after a frequency (tone) measurement has been successfully completed. the n otone timer is a one-shot timer being reset only by successful tone measurements. if the quality of the received signal drops to an unusable level the n otone timer will start its run-down. on completion of the preset period, the n oton e timer period expired bit in the status register and the interrupt (when enabled, table 2 ) are set. upon detection of the interrupt, the status register should be read by the m controller to ascertain the source of the interrupt. the n oton e timer period expired bit is cleared: i by a read of the status register or, ii new n otone timer information or, iii general reset command this timer is set to 00 h (0ms) by a general reset command. no signal the n otone timer can only start its run down on completion of a valid frequency measurement. no signal after a valid tone measurement the timer will start to run down when the last rx tone measurement complete bit is set. at the end of the primed period the n oton e timer period expired bit in the status register and the interrupt will be set. the following situations may be encountered by the n otone timer circuitry: signal fades after a valid tone measurement the timer will start to run down when the signal becomes unreadable to the device. at the end of the primed period the n oton e timer period expired bit in the status register and the interrupt will be set. signal appears after the timer has started if the frequency measurement is more than 75% complete when the timer period expires, neither the n otone bit nor the interrupt will be set unless that frequency measurement is subsequently aborted. table 6 rx n otone timer settings
11 controlling protocol ...... write to general purpose timer register C a/c 36 h followed by 1 byte of command data. setting msb 76 5 4 0000 321 0 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 function/period transmitted bit 7 first these 4 bits must be 0 high/extended mid band band reset timer and start timing period of 0 0 " 10 ms 1% 20 ms 1% 20 " 40 " 30 " 60 " 40 " 80 " 50 " 100 " 60 " 120 " 70 " 140 " 80 " 160 " 90 " 180 " 100 " 200 " 110 " 220 " 120 " 240 " 130 " 260 " 140 " 280 " 150 " 300 " operation of the general purpose timer this timer, which is not dedicated to any specific function within the FX803, can be employed within the dbs 800 system to indicate time-elapsed periods of between 10ms and 150ms in the high/extended band, 20ms and 300ms in the mid band, to the m controller. setting of the timer is by loading a single-byte data word via the c-bus, as indicated in table 7 (left), to the FX803 via the command data line. the timer will be reset and the run-down started on completion of timer data word loading. when the programmed time period has expired, the general purpose timer expired bit (bit 2) in the status register and the interrupt (if enabled) are set. the general purpose timer expired bit is cleared: i by a read of the status register, or ii new g/p timer information, or iii general reset command. when the programmed time period has expired, this timer will reset, restart and continue sequencing until; i new g/p timer information is written, or ii a general reset command. the general purpose timer expired bit and the interrupt will remain set until cleared. this timer is set to 00 h (0ms) by a general reset command. powersaved section instruction source table tone encoder 1 tx tone gen.1 reg. (34 h ) all bits = 0 4 tone encoder 2 tx tone gen.2 reg. (35 h ) all bits = 0 5 summing amplifier this action is automatic when both tone encoders are in the powersave condition. table 8 FX803 powersave functions powersave various sections of the FX803 can be placed independently into a power economical condition. table 8 (below) gives a brief summary of the inactive, power-economical states available to the FX803. powersave conditions xtal/clock and c-bus : this circuitry is always active, on all dbs 800 microcircuits, under any powered/powersaved conditions. table 7 general purpose timer settings
12 controlling protocol ...... n otone timer period expired enabled: by control register bit 5. set: when the preset notone flag is set. identified: by status register bit 1. cleared: by reading the status register. g/purpose timer period expired enabled: by control register bit 6. set: when the general purpose timer has timed out. identified: by status register bit 2. cleared: by reading the status register. rx tone measurement complete enabled: by control register bit 5. set: when an rx frequency measurement has been successfully completed. identified: by status register bit 0. cleared: by reading the status register. on recognition of the read status command byte, the interrupt output is cleared, the status bits are transferred to the m controller via the c-bus reply data line and the internal status bits are cleared. operational recommendations it is recommended that, following initial system power-up a general reset command is sent to the FX803. receive sequence 1. send control command for rx: select midband/highband and digital filter length. 2. disable transmitters, if desired by writing to tone frequency registers. 3. prime the n otone timer by sending the required period byte. 4. enable decoder interrupts as desired. 5. when a valid tone has been detected by a successfully completed measurement the status register is set to tone measurement complete and an interrupt sent to the m c. 6. the m c examines the status register, if tone measurement is complete, reads in the rx tone frequency in the form n + r (figure 6). 7. rx tone measurement complete interrupts are periodically sent to the m c unless n otone is detected, in which case a n otone interrupt is sent. transmit control sequence 1 . set tone frequency generators to v bias (setting both tone generators (bit 13 = 1)) during the transmitter initialization period. 2 . send control command for tx: select sum/switched sum o/p and audio switch states. 3 . send general purpose (gp) timer information for the v bias (n otone ) transmitter initialization period (step 1). this will initiate the timer. 4. enable the general purpose timer interrupt. 5. m c waits for gp timer expired; reads the status register to check interrupt due to timer; resets the status bit. if required, the m c sends the next timer period followed by the next tone(s) frequency information. a new timer period sent will reset the timer, otherwise the timer is self-sequencing. 6. the m c monitors the interrupts and repeats 5 & 6 as required. 7. after last loaded tone the m c turns off the tone generator(s) by setting tone outputs to v bias (n otone ) (tables 4 and 5). general reset upon power-up the bits in the FX803 registers will be random (either 0 or 1). a general reset command (01 h ) will be required to reset all microcircuits on the c-bus, and has the following effect upon the FX803. control reg. set as 00 h status reg. bits 0, 1, 2.) set as 00 h n otone timer reg. set as 00 h tone gen. 1 reg. (2 bytes) set as 0000 h tone gen. 2 reg. (2 bytes) set as 0000 h gen/purpose reg. set as 00 h sets the FX803 to: encoder high band (625hz to 3000hz) C with interrupts disabled, both timers set to 00 h . it is recommended that both timers are set-up before interrupts are enabled, to prevent initial, undesired interrupts. glossary of abbreviations below is a list of abbreviations used within this data sheet. f xtal xtal/clock frequency s input audio input signal f tone tone frequency interrupt requests an interrupt (irq), when enabled, is provided by the FX803 to indicate the following conditions to the m controller.
13 timing information 70% v dd 30% v dd t cl t ch t cds t cdh t rds t ck t rdh serial clock (from m c) command data (from m c) reply data (to m c) parameter min. typ. max. unit t cse 2.0 C C m s t csh 4.0 C C m s t csoff 2.0 C C m s t nxt 4.0 C C m s t ck 2.0 C C m s t ch 500 C C ns t cl 500 C C ns t cds 250 C C ns t cdh 0CCns t rds 250 C C ns t rdh 50.0 C C ns t hiz C C 2.0 m s notes (1) command data is transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the FX803 msb (bit 7) first, lsb (bit 0) last. (2) data is clocked into the FX803 and into the m controller on the rising serial clock edge. (3) loaded data instructions are acted upon at the end of each individual, loaded byte. (4) to allow for differing m controller serial interface formats, the FX803 will work with either polarity serial clock pulses. timing diagrams figure 7 shows the timing parameters for two-way communication between the m controller and the FX803 on the c-bus. figure 8 shows, in detail, the timing relationships for c-bus information transfer. serial clock command data t cse t nxt t csoff t csh t hiz address/command byte first data byte last data byte 76543210 76543210 76543210 76543210 msb lsb chip select last reply data byte t nxt t ck reply data 76543210 msb lsb first reply data byte logic level is not important fig.7 c-bus timing information not to scale fig.8 c-bus timing relationships not to scale
14 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation @ t amb 25 c 800mw max. derating 10mw/ c operating temperature range: FX803j -40 c to +85 c (cerdip) FX803dw/lg/ls -40 c to +85 c (plastic) storage temperature range: FX803j -55 c to +125 c (cerdip) FX803dw/lg/ls -40 c to +85 c (plastic) operating limits all device characteristics are measured under the following conditions unless otherwise specified: v dd = 5.0v. t amb = 25 c. xtal/clock (f xtal ) = 4.032mhz. audio level 0db ref: = 308mvrms @ 1khz (60% deviation, fm) . noise bandwidth = 5.0khz band-limited gaussian. characteristics see note min. typ. max. unit static values supply voltage 4.5 5.0 5.5 v supply current (decoder + both timers) C 2.0 C ma (decoder + both timers + one tx only) C 4.0 C ma (all functions enabled) C 5.0 C ma analogue impedances (rx) audio input C 20.0 C m w summing amp input C 20.0 C m w switch C 1.0 C k w tones 1 and 2 outputs C 10.0 C k w cal/cues output C 5.0 C k w summing outputs C 10.0 C k w dynamic values digital interface input logic 1 1 3.5 C C v input logic 0 1 C C 1.5 v output logic 1 (ioh = -120 m a) 2 4.6 C C v output logic 0 (iol = 360 m a) 3 C C 0.4 v i out tristate (logic 1 or 0) 3 C C 4.0 m a input capacitance 1 C C 7.5 pf iox (v out = 5.0v) 4 C C 4.0 m a overall performance rx C decoding high-band sensitivity C -20.0 C db tone response time good signal 5 C C 30.0 ms tone-to-noise ratio = 0db 5, 6 C C 40.0 ms frequency band 625 3000 hz measurement resolution C 0.2 C % measurement accuracy 9 C 0.5 C %
15 specification ...... characteristics see note min. typ. max. unit rx C decoding ...... mid-band sensitivity C -20.0 C db tone response time good signal 7 C C 60.0 ms tone-to-noise ratio = 0db 6, 7 C C 80.0 ms frequency band 313 1500 hz measurement resolution C 0.2 C % measurement accuracy 9 C 0.5 C % extended-band sensitivity C -20.0 C db tone response time good signal 5 C C 20.0 ms frequency band 1250 6000 hz measurement resolution C 0.2 C % measurement accuracy 9 C 0.5 C % tx C encoders 1 and 2 tone frequency 208 3000 hz period (1/f tone ) error C C 1.0 m s tone amplitude -1.0 C 1.0 db total harmonic distortion C C 5.0 % rise time to 90% C 3/f tone C secs fall time to 10% 8 C C 5.0 ms frequency change time C 3/f tone C secs timers general purpose timing period range high-band 10.0 150 ms mid-band 20.0 300 ms rx n otone timing period range high-band 20.0 300 ms mid-band 40.0 600 ms xtal/clock frequency (f xtal ) 3.9 C 6.0 mhz notes 1. device control pins; serial clock, command data, and cs. 2. reply data output. 3. reply data and irq outputs. 4. leakage current into the off irq output. 5. measurement period = 9.125ms. 6. decode probability = 0.993. 7. measurement period = 18.250ms. 8. when set to powersave. 9. for a good input signal. 10. the use of the FX803 at xtal/clock frequencies above 4.0mhz will cause a shift in the overall performance parameters.
handling precautions the FX803 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. package outlines the FX803 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. FX803j 24-pin cerdip dil (j4) FX803dw 24-pin plastic s.o.i.c. (d2) not to scale max. body length 32.00mm max. body width 13.36mm not to scale max. body length 15.57mm max. body width 7.59mm cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. FX803ls 24-lead plastic leaded chip carrier (l2) not to scale max. body length 10.40mm max. body width 10.40mm FX803lg 24-pin quad plastic encapsulated bent and cropped (l1) not to scale max. body length 10.25mm max. body width 10.25mm ordering information FX803dw 24 pin plastic s.o.i.c. (d2) FX803j 24-pin cerdip dil (j4) FX803lg 24-pin encapsulated bent and cropped (l1) FX803ls 24-lead plastic leaded chip carrier (l2)

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